library ieee; 
use ieee.std_logic_1164.all; 

entity decoder_3 is
port ( SEL : in std_logic_vector(2 downto 0);
outlet : out std_logic_vector(3 downto 0)
);
end decoder_3;


architecture arqdecoder of decoder_3 is
begin
with SEL select
outlet <= "0001" when "100",
"0010" when "101",
"0100" when "110",
"1000" when "111",
"0000" when others;
end arqdecoder;

